Atrisa GTM brain

category

market profile

• text: Analog engineers iterate among schematics, simulations and debugging while balancing performance, power and area.
• text: The market includes EDA incumbents adding analog design agents and startups building automated simulation and optimization loops.
• text: A founder interview describes early pricing thinking as seat based with a usage component, not a confirmed public price.

personas

• title: Analog IC design lead
  pains:

  • Serial schematic edits, simulations and failure investigations slow iteration
  • Must hit circuit specifications across operating conditions with limited expert time
• title: VP of chip engineering
  pains:

  • Specialist analog capacity limits parallel design projects
  • Knowledge gained debugging a circuit stays with individual engineers
• title: Analog CAD methodology engineer
  pains:

  • Needs automation compatible with existing design tools and simulators
  • Must evaluate failure recovery and verify results before use in production

icp

• text: Fabless semiconductor firms and chip design teams working on analog or mixed-signal blocks with SPICE workflows are the likely core accounts.
• text: Teams running repeated design and debug loops and sharing circuit knowledge across engineers are plausible pilot candidates; company size is unspecified.

message pillars

• text: Position the copilot as an amplifier of the analog team.
• text: Reduce repetitive circuit design and investigation work.
• text: Keep engineering judgment central.

objections

• objection: Can it meet our specifications across process and operating corners?
  response: Pilot a bounded block and compare verified simulations and corner behavior with the established engineering flow.
• objection: Will it work with our EDA environment?
  response: Confirm exact simulator and tool support in the demo; the company describes working with existing tools but does not list integrations.
• objection: Will the productivity claim hold on our designs?
  response: Measure engineering time and verified iterations on a representative task against a baseline.

competitors

• name: Cadence
  website: https://www.cadence.com/en_US/home/resources/white-papers/using-ai-for-analog-design.html
  why: Virtuoso AI Studio and agents address analog design workflows.
• name: circuitEvolve
  website: https://www.circuitevolve.com/
  why: AI optimization from analog specifications to layout-ready design.
• name: Tattvam AI
  why: AI-driven circuit design automation startup.

influencers

• name: Rithik Jain
  url: https://swethasrinivasan.substack.com/p/the-dark-art-atrisa-and-the-case
  why: Co-founder explains the product and early commercial thinking in an interview.

keywords

• analog circuit design AI
• analog IC design automation
• SPICE simulation AI
• mixed signal design copilot
• analog circuit debugging
• EDA AI agents

voice

• Engineer-focused
• Ambitious
• Practical about simulation and debugging

signals

• text: A semiconductor team is hiring analog and mixed-signal engineers or expanding design capacity.
• text: A design team reports repeated simulator setup and debugging bottlenecks.
• text: A methodology group is evaluating agents that can interact with existing circuit simulators.

stack

• SPICE
• Python
• PyTorch

hiring

• Founding Analog Design Engineer
• Founding AI / ML Engineer

pricing

motion

channels

• demo requests
• LinkedIn
• YouTube

confidence

Founders

• name: Sayan Mitra
  title: Founder/CEO
  role: CEO
  bio: CEO @ Atrisa | Ex Research Engineer @ KLA Semiconductors | Electrical Engineering @ IIT Madras
• name: Rithik Jain
  title: Founder
  role: Founder
  bio: COO @ Atrisa | Ex-PhD @ UW-Madison
• name: Atman Kar
  title: Founder/CTO
  role: CTO
  bio: CTO @ Atrisa | Ex-Texas Instruments Engineer